1. Dvteclipse
  2. Dvt Eclipse Verdi
  3. Eeuop
  • Dvteclipse工具简介(一) 发表于 2017年9月2日 由 卢 骏 这几天,在公司体验了开发verilog,systemverilog,UVM的IDE,真是不用不知道,一用吓一跳,该IDE的功能真是太强大了,简直是开发verilog,systemverilog,UVM的神器。.
  • External Install Button Design and Verification Tools (DVT) is an integrated development environment (IDE) for the design and verification engineers working with SystemVerilog, Verilog, VHDL, e, UPF, CPF, SLN, PSS, SDL. Including Universal Verification Methodology (UVM) support.
  • DVT Eclipse IDE For design and verification engineers who are working with Verilog, SystemVerilog, Verilog AMS, VHDL, UPF, CPF, e Language, PSS, SLN, or SDL, the Design and Verification Tools (DVT) Eclipse IDE is an integrated development environment (IDE) that significantly improves productivity.

Dvteclipse.com DA: 18 PA: 18 MOZ Rank: 36 DVT Eclipse IDE For design and verification engineers who are working with Verilog, SystemVerilog, Verilog AMS, VHDL, UPF, CPF, e Language, PSS, SLN, or SDL, the Design and Verification Tools ( DVT) Eclipse IDE is an integrated development environment (IDE) that significantly improves productivity. E was first developed in 1992 in Israel by Yoav Hollander for his Specman software. In 1995 he founded a company, InSpec (later renamed Verisity), to commercialize the software.The product was introduced at the 1996 Design Automation Conference. Verisity has since been acquired by Cadence Design Systems. Main features of e are:. Random and constrained random stimulus.

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Designed byYoav Hollander
First appeared1992
Stable release
Filename extensions.e
WebsiteTWiki @ eda.org

e is a hardware verification language (HVL) which is tailored to implementing highly flexible and reusable verification testbenches.



e was first developed in 1992 in Israel by Yoav Hollander for his Specman software. In 1995 he founded a company, InSpec (later renamed Verisity), to commercialize the software. The product was introduced at the 1996 Design Automation Conference.[1] Verisity has since been acquired by Cadence Design Systems.



Main features of e are:

  • Random and constrained random stimulus generation
  • Functional coverage metric definition and collection
  • Temporal language that can be used for writing assertions
  • Aspect-oriented programming language with reflection capability
  • Language is DUT-neutral in that you can use a single e testbench to verify a SystemC/C++ model, an RTL model, a gate level model, or even a DUT residing in a hardware acceleration box (using the UVM Acceleration for e Methodology)
  • Can create highly reusable code, especially when the testbench is written following the Universal Verification Methodology (UVM)
    • Formerly known as e Re-use Methodology (eRM)
    • UVM e library and documentation can be downloaded here: UVM World

Language Features[edit]

The e language uses an aspect-oriented programming (AOP) approach, which is an extension of the object-oriented programming approach to specifically address the needs required in functional verification. AOP is a key feature in that it allows for users to easily bolt on additional functionality to existing code in a non-invasive manner. This permits easy reuse and code maintenance which is a huge benefit in the hardware world, where designs are continually being tweaked to meet market demands throughout the project lifecycle. AOP also addresses cross cutting concerns (features that cut across various sections of the code) easily by allowing users to extend either specific or all instances of a particular struct to add functionality. Users can extend several structs to add functionality related to a particular feature and bundle the extensions into a single file if desired, providing for more organized file partitioning.


Executable e code is enclosed within code-segment markers <' and '>:



e also has two kinds of classes:

  • Dynamic classes are labeled with the keyword 'struct'. Structs are used for creating data that only exists temporarily and may be cleaned by the garbage collector.
  • Static classes are labeled with the keyword 'unit'. Units are used for creating the permanent testbench structure.

A class may contain fields, methods, ports and constraints. Fields can be of type integer, real, enum, string and even complex objects. The code segment shows a unit called 'environment_u' being instantiated within the e root 'sys'. This environment_u class contains a list of 5 packet_s objects and this packet_s class contains two fields and a method.




In e each field is randomized by default. Field randomization can be controlled by hard constraints, soft constraints or even be turned off completely. Soft constraints are used as the default constraints, and may be automatically overridden by the test layer if a conflict occurs. Otherwise it behaves like a regular constraint.



e supports assertions with temporal expressions. A temporal expression is used at the same syntactic level as fields and methods and is thereby declarative by nature. A temporal expression describes timed behavior.



e supports coverage that are grouped according to their sampled event and those groups are internally structured with items. Items can be simple items or complex items such as crossed items or transitional items.


Messaging & Reporting[edit]

Messaging within e can be done with various methods.


Interfacing With Other Languages[edit]

An e testbench is likely to be run with RTL or higher-level models. Bearing this in mind, e is capable of interfacing with VHDL, Verilog, C, C++ and SystemVerilog.

Dvt eclipse uvm

Example of an e <-> Verilog Hookup[edit]

Aspect-Oriented Programming Support in e[edit]

The process of functional verification requires to raise the level of abstraction of any Design Under Test (DUT) beyond the RTL level. This necessity calls for a language that is capable of encapsulating data and models, which is readily available in object-oriented languages. To address this need has been designed to be e an object-oriented language and on top of that has been augmented with aspect-oriented mechanisms that facilitate not only writing highly flexible and reusable testbenches, but also helps verification engineers by enabling to patch discovered RTL bugs without having to rewrite or touch any of the already existing code base.
Aspect-oriented programming in e allows verification engineers to structure their testbench in aspects. An object is therefore the sum of all its aspects, which may be distributed over multiple files. The following sections illustrate basic aspect-oriented mechanisms in e.

Subtyping Mechanism[edit]

Subtyping is the prime example of what object-oriented languages without aspect-oriented features can not accomplish. Subtyping allows a verification engineer to add functionality to an already defined/implemented class without having to derive from a base class. The following code shows the original implementation of a base-class and how it is extended. Once the extension took place, all base-class objects contain the extensions as well. The constraints given in the two different subtypes would usually cause a contradiction, however both subtypes are handled separately and thus each subtype yields a different constraint calculation.

Subtyping Mechanism Example[edit]

Extending Methods[edit]

The original unit definition is given in file1.e. The aspect-oriented mechanism used in this example shows how to execute code before and after an already implemented method.

Dvt Eclipse Verdi

Method Extension Example[edit]

Dvt eclipse svn


  • The e Hardware Verification Language, Sasan Iman and Sunita Joshi, Springer, May 28, 2004
  • Aspect-Oriented Programming with the e Verification Language, David Robinson, 2007
  1. ^Samir Palnitkar: Design verification with e, Prentice Hall PTR. October 5, 2003. ISBN978-0-13-141309-2


  • http://www.eda.org/twiki/bin/view.cgi/P1647/WebHome IEEE 1647
  • http://www.deepchip.com/items/0488-05.html (good feedback from users on their experiences with the e language)
  • Janick Bergeron: Writing Testbenches: Functional Verification of HDL Models, Second Edition, Kluwer Academic Publishers, 2003, ISBN1-4020-7401-8


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